FBGA (Fine Pitch BGA)
3D Technology - Stacked CSP
Chip on Film (COF)
Quad Flat No Lead Package (QFN)
Low-Profile Quad Flat Pack (LQFP)
Multi-Chip & Stacked Leadframe
Small Outline Package (SOP)
TSOP-I/TSOP-II/TSOP-II (LOC)
FC DFN/QFN (Flip chip DFN/QFN)
FC CSP (Flip chip CSP)
WLCSP (Wafer Level Chip Scale Package)
FPS (Finger Print Sensor)
ChipMOS employs the conventional TSOP package as a carrier with embedded substrate to play the roles of chip support and the circuit re-distribution, and to accommodate more than one chip into the TSOP pin assignment. This technology provides a flexible, easy and low cost alternative to the concept of "SOC."
Applications
The main application of this technology is for memory devices for notebook computers, personal computers, audio and video products and wireless communication products.
Features
ChipMOS' TSOP package with substrate provides:
- Conventional TSOP I & II family outline
- Flexible to change package type
- Substrate as chip support and the circuit re-distribution
- 1.0 mm body thickness
- 0.127 mm leadframe thickness
- Customized leadframe & substrate design available
- Substrate selection for various chip sizes
Reliability
| Moisture sensitivity | JEDEC Level 3 | - |
| High Temp. Storage Test | 150°C | 1000 hr. |
| Temperature Cycling | -55°C/125°C | 500 cycles |
| Pressure Cooker Test | 121°C/100% RH/2 atm | 240 hr. |
| Temp. & Humidity Test | 85°C/85% RH | 1000 hr. |
Process Highlights
| Wafer Backside grinding | Available |
| Die Thickness | 6 - 8 mil |
| Solder Plating | 85Sn/15Pb |
| Marking | Laser |
| Coplanarity | < 4 mil |
| Lead Inspection | Laser/Optical |
| Packing/Shipping | Bar code, dry packing |
Shipping
JEDEC standard tray