FBGA (Fine Pitch BGA)
3D Technology - Stacked CSP
Chip on Film (COF)
Quad Flat No Lead Package (QFN)
Low-Profile Quad Flat Pack (LQFP)
Multi-Chip & Stacked Leadframe
Small Outline Package (SOP)
TSOP-I/TSOP-II
FC DFN/QFN (Flip chip DFN/QFN)
FC CSP (Flip chip CSP)
WLCSP (Wafer Level Chip Scale Package)
FPS (Finger Print Sensor)
The TSOP (Thin Small Outline Package) package provides the advantages of thin profile, low manufacturing cost, and mature packaging technology. There are two different configurations in package outline: TSOP-I, which has external leads at the short package edges, and TSOP-II, which has leads at the long package edges. These 1.0 mm-thick packages can operate reliably in a variety of environments. Therefore, the packages are widely adapted in electronic products. ChipMOS offers several packages, including:
| Package | Package Size | Lead Counts |
| TSOP-I | 12 x 20.0 mm | 48 |
| 14 x 20.0 mm | 56 |
| Package | Body Width | Lead Counts |
| TSOP-II | 400 mil | 54, 66, 86 |
Applications
TSOP packages apply to portable electronic products, cell phones, PC (PCMCIA) cards, and memory modules, etc.
Features
- Enhanced design for memory application
- Stacked/multi-chip application
- Shrink TSOP
Reliability
| Moisture sensitivity | JEDEC Level 2 JEDEC Level 1 |
TSOP-I / TSOP-II TSOP-II (LOC) |
| High Temp. Storage Test | 150°C | 1000 hr. |
| Temperature Cycling Test | -65°C/150°C | 500 cycles |
| Thermal Shock Test | -65°C/150°C | 500 cycles |
| Pressure Cooker Test | 121°C/100% RH/2 atm | 240 hr. |
| Temp. & Humidity Test | 85°C/85% RH | 1000 hr. |
| Highly Accelerated Stress Test | 130°C/85% RH/bias | 100 hr. |
Process Highlights
| Wafer Backside grinding | Available |
| Die Thickness | 10~16 mil |
| Solder Plating | 85Sn/15Pb |
| Marking | Laser |
| Coplanarity | < 4 mil |
| Lead Inspection | Laser/Optical |
| Packing/Shipping | Bar code, dry packing |