The TSOP (Thin Small Outline Package) package provides the advantages of thin profile, low manufacturing cost, and mature packaging technology. There are two different configurations in package outline: TSOP-I, which has external leads at the short package edges, and TSOP-II, which has leads at the long package edges. For advanced applications, the lead-on-chip (LOC) structure has been devised with the inner lead attached onto the chip surface for the central-pad memory products in a TSOP-II package that is called TSOP-II LOC package. These 1.0 mm-thick packages can operate reliably in a variety of environments. Therefore, the packages are widely adapted in electronic products. ChipMOS offers several packages, including:
| Package | Package Size | Lead Counts |
| TSOP-I | 8 x 13.4 mm | 28, 32 |
| 8 x 20.0 mm | 32 | |
| 12 x 20.0 mm | 48 |
| Package | Body Width | Lead Counts |
| TSOP-II | 400 mil | 40/44, 44, 50, 54, 66, 86 |
| TSOP-II LOC | 400 mil | 40/44, 54, 54/66, 54/86 |
Applications
TSOP packages apply to portable electronic products, cell phones, PC (PCMCIA) cards, and memory modules, etc.
Features
- Enhanced design for memory application
- Stacked/multi-chip application
- Shrink TSOP
Reliability
| Moisture sensitivity | JEDEC Level 2 JEDEC Level 1 |
TSOP-I / TSOP-II TSOP-II (LOC) |
| High Temp. Storage Test | 150°C | 1000 hr. |
| Temperature Cycling Test | -65°C/150°C | 500 cycles |
| Thermal Shock Test | -65°C/150°C | 500 cycles |
| Pressure Cooker Test | 121°C/100% RH/2 atm | 240 hr. |
| Temp. & Humidity Test | 85°C/85% RH | 1000 hr. |
| Highly Accelerated Stress Test | 130°C/85% RH/bias | 100 hr. |
Process Highlights
| Wafer Backside grinding | Available |
| Die Thickness | 10~16 mil |
| Solder Plating | 85Sn/15Pb |
| Marking | Laser/IR Ink |
| Coplanarity | < 4 mil |
| Lead Inspection | Laser/Optical |
| Packing/Shipping | Bar code, dry packing |