IC packaging is the essential technology that distributes electrical signals from a silicon chip onto the printed circuit board via different types of interconnection methods while provides protection against environmental stresses. A variety of IC packaging technologies is available from ChipMOS to meet numerous end product requirements, including low profile, small foot-print, light weight, efficient thermal dissipation, and better performance in electrical properties and reliability.

ChipMOS offers a broad range of package families designed to provide our customers with an array of packaging solutions. The packages available include leadframe-based packages, such as the small outline package (SOP), thin small outline package (TSOP) and quad flat package (LQFP/TQFP); and the substrate-based packages, such as FBGA, VFBGA, stacked CSP, TFBGA, LGA, COG and COF. Aimed for optimum device performance, ChipMOS employs state-of-the-art Computer Aided Engineering (CAE) simulation techniques, for both electrical and thermal analyses, to facilitate package design and manufacturing parameter optimization. Customers are able to make good use of ChipMOS' technical capability by inputting their information on the "Design Center" or "Package Characterization" pages of our website.

To be competitive and provide a leading edge advantage to our clients, ChipMOS, working jointly with our material and equipment vendors and customers, has focused significant resources on the development of advanced packaging technologies, including: Wafer Level CSP, 3D technology, Flip Chip CSP, environmentally friendly green package, System-in-Package technology, Known Good Die technology, MEMS and display driver IC(DDI) packages such as chip on film (COF) and chip on glass (COG).

Mechanical samples are available from our shop floor for trial run and equipment parameter setting.